RISC-V is an instruction set. That is a specification of the basic instructions a CPU can perform, eg. what your C-compiler emits. But unlike the ARM instruction set,used by your phone or tablet, or the x86 instruction set, used by your computer and server RISC-V is free and open. That is you're free to download the specification from riscv.org, build your own CPU and even share your work like many have already done. There is already upstream support many of the tools we take for granted: GCC, LLVM, Rust, Go, glibc, u-boot, coreboot, Linux, FreeBSD etc. but there is unfortunately not much real hardware available yet, so trying it out can feel like a challenge.
After a basic introduction I plan to get everyone set up so we can program the GD32VF108 RISC-V microcontroller on the Longan Nano board. One of the first pieces of hardware you can actually buy on a hobby budget. Hopefully we can find enough boards for everybody during the workshop and maybe even have a few to sell afterwards.
Next I'll show how to run Fedora Rawhide or Debian Sid in Qemu on your computer, so you can follow or join the porting effort and even try out your own favourite piece of code on RISC-V. This requires a non-ancient Qemu, so please bring a recent Linux distro or do your own experiments on MacOS or maybe even Windows' WSL. If time permits we'll also build our own "BIOS" and Linux kernel for it. I'll also bring the HiFive Unleashed that I won.
Hosts for Getting started with RISC-V:
Metadata for Getting started with RISC-V
To be recorded: NoURLs for Getting started with RISC-V
Github: https://github.com/esmil/gd32vf103inator
Github: https://github.com/esmil/riscv-linux
Schedule for Getting started with RISC-V
- Monday, Aug 17th, 2020, 11:00 (CEST) - Monday, Aug 17th, 2020, 14:00 (CEST) at Workshop Room